The present invention relates to an avalanche photo-diode and a fabrication method thereof. More particularly the invention pertains to a photo-detector using a semiconductor, and more particularly to a reliable avalanche photo-diode of a mesa structure having a low dark current.
An avalanche photo-diode for use in optical communication and the like is a semiconductor photo-detector whose photo-detecting sensitivity is enhanced by providing a layer for avalanche-multiplying a carrier generated by opto-electronic conversion in addition to an optical absorption region for carrying out opto-electronic conversion. Such an avalanche photo-diode indispensably requires a low dark current and high reliability.
Semiconductor photo-detectors, mostly formed of chemical compound semiconductors, can be broadly classified into planar structure and mesa structure photo-detectors. A mesa structure photo-diode is a diode having a structure in which a mesa is formed over a substrate and the mesa contains a pn junction. The mesa structure, though simple to fabricate, has disadvantages of low reliability and a high dark current. The reasons include the high electric field intensity of the pn junction emerging on a side surface of the mesa, a tendency for electric fields to concentrate on the periphery (edge) of the junction, and that for minute leak current paths to be readily formed by surface state and any surface defect formed on an exposed surface.
On the other hand, a planar structure photo-diode has a structure in which a pn junction region having a high electric field intensity is formed within a crystal, and the part exposed on the surface has a lower electric field intensity, resulting in higher reliability and a lower dark current. However, its fabrication process is complex, sometimes prohibitively difficult depending on the element structure, resulting in a disadvantage of poor practical usefulness.
As a method to alleviate the above-noted disadvantages of mesa-structured semiconductor photo-detectors, a structure to cover the side surface of the mesa with a burying-layer is disclosed in the Japanese Patent Laid-open (Kokai) No. Hei 6-232442. The technique disclosed therein will be described below with reference to FIG. 10. There is used a process in which, after mesas are formed on layers 82 through 88 crystal-grown over a substrate 81, a burying-layer 89 of a high-resistance semiconductor is grown over a side surface 90 and a periphery 91 of the mesa. A pn junction surface is formed between the layer 83 and the layer 84. In addition to them, electrodes 92 and 93 and an anti-reflection layer 94 are formed.
Since the mesa side surface 90 is covered by the burying-layer 89 in this structure, leak currents attributable to the surface state or any surface defect are less than they would be where the burying-layer 89 is absent.
However, as the electric field intensity around the pn junction emerging on the mesa side surface 90 remains strong in the above-described structure, it is difficult to achieve a low enough dark current or high enough reliability to make the photo-diode adequate for practical use. Especially in an element having a pn junction with a high electric field intensity, such as an avalanche photo-diode, a breakdown (edge breakdown) tends to occur around the junction, inevitably leading to a low rate of multiplication and poor uniformity.
An object of the present invention is to provide a highly reliable mesa-structured avalanche photo-diode using a novel structure capable of keeping the dark current low and a fabrication method therefor.
In order to achieve the above-stated object, an avalanche photo-diode according to the invention has an absorption layer for absorbing light to generate a carrier, a multiplication layer for multiplying the generated carrier, and a field control layer inserted between the absorption layer and the multiplication layer, wherein a first mesa including at least part of the multiplication layer and part of the field control layer is formed over a substrate, a second mesa including another part of the field control layer and the absorption layer is formed over the first mesa, and the area of the top of the first mesa is greater than that of the bottom of the second mesa. A semiconductor layer is formed over the part of the first mesa top surface not covered by the second mesa and the side surface of the second mesa. In the following description, the semiconductor layer will be referred to as the burying-layer.
Further in the avalanche photo-diode, the thickness of the part of the field control layer included in the first mesa is less than the thickness of the field control layer spanning between the first mesa and the second mesa as an additional characteristic.
In the avalanche photo-diode, a semiconductor layer is formed over the part of the first mesa top surface not covered by the second mesa and over the side surface of the second mesa as another additional characteristic. In the following description, if the thickness of the semiconductor layer is large enough to be approximately equal to the height of the second mesa, it will be referred to as a burying-layer, or if it is formed thin for the purpose of protecting the mesa surface, it will be referred to as a semiconductor protection film. It is preferable for this protection film to be a thin film, and to be an insulator or a semiconductor.
A possible structure of a structure avalanche photo-diode according to the invention having the above-stated characteristics will be shown in FIG. 1. While a more detailed description will be given afterwards, in FIG. 1, reference numeral 1 denotes an n-type InP substrate; 2, an n-type InAlAs buffer layer; 3, an n-type InAlAs/InGaAs multiplication layer; 4, a p-type InAlAs field control layer; 5, a p-type InGaAs absorption layer; 6, a p-type InAlAs cap layer; and 7, a p-type InGaAs contact layer.
A pn junction surface is formed on the boundary between the n-type multiplication layer 3 and the p-type field control layer 4. With the middle plane of the thickness of the field control layer 4 as the border, the layers below that plane constitute a first mesa 18 containing the pn junction while the layers above the constitute a second mesa 13.
The area of the top of the mesa 18 is greater than the area of the bottom of the mesa 13. Therefore, the top surface of the mesa 18 has a part not covered by the bottom of the mesa 13. In the following description, this part will be referred to as the peripheral surface of the second mesa (denoted by a reference numeral 15 in FIG. 1).
A burying-layer (regrown layer) 8 is formed over a side surface 14 and the peripheral surface 15 of the mesa 13. The burying-layer 8, whose carrier concentration is set substantially equal to or below that of the absorption layer 5, has a high resistance.
The above-described structure can serve to reduce the electric field intensity around the pn junction. The principle of this effect will be explained with reference to FIG. 2. Electric field designing is essential for an avalanche photo-diode. The electric field intensity distribution in the multiplication layer 3, the field control layer 4, the absorption layer 5 in the mesa center represented by a broken line in FIG. 1 is as represented by a one-dot chain line in FIG. 2. Thus the electric field intensity is set higher in the multiplication layer 3 to induce avalanche multiplication and, conversely, that in the absorption layer 5 is set lower to avoid avalanche multiplication. Such a electric field intensity distribution can be formed by appropriately regulating the carrier concentration in the field control layer 4. Incidentally, as the carrier concentration in the cap layer 6 is set substantially higher than that in the absorption layer 5, no electric field is formed beyond the absorption layer 5.
Since the electric field intensity in the multiplication layer 3 is extremely high in this state, reliability will drop if it is exposed as it is on the element surface. According to the invention, with a view to securing sufficient reliability, note is taken of the possibility to reduce the electric field intensity of the multiplication layer 3 exposed on the surface.
The electric field intensity of the multiplication layer 3 can be varied by regulating either the concentration or the thickness of the field control layer 4. More specifically, if for example the concentration of the field control layer 4 is reduced to xc2xd or, without changing the concentration, its thickness is reduced to xc2xd, the electric field intensity rise in the field control layer 4 will be reduced to xc2xd of the previous rise, and this eventually serves to reduce the electric field intensity in the multiplication layer 3.
Therefore, if the thickness of the field control layer 4 in the mesa periphery represented by a broken line in FIG. 1, i.e. the part to constitute the peripheral surface 15 of the mesa 13, is reduced and a burying-layer (regrown layer) 8 having a relatively low carrier concentration is formed over it, the electric field intensity distribution near the surface will be as represented by a solid line in FIG. 2, and this means the electric field intensity in the multiplication layer 3 can be reduced.
The proper thickness of the field control layer 4 in the part of the mesa peripheral surface 15 can be determined according to the electric field design of the element, and obviously it is not limited to the xc2xd reduction mentioned above. It is also to be noted that the thickness of the field control layer 4 in the part of the mesa peripheral surface 15 may increase toward the substrate 1. In such a case, too, a similar effect can be achieved by setting that thickness smaller than that of the field control layer 4 spanning between the mesa 13 and the mesa 18, i.e. that of the field control layer 4 at the mesa center.
Further, if the thickness of the field control layer at the mesa center is set greater, the above-noted effect can still be achieved even in the absence of the burying-layer 8.
FIG. 3 shows the result of computation of the electric field distribution in an element according to the present invention. In this case, the thickness of a field control layer 204 (p-type, 7xc3x971017 cmxe2x88x923 in impurity concentration) is 0.05 xcexcm in the mesa part and 0.03 xcexcm on the mesa periphery. The electric field distribution in a multiplication layer 203, the field control layer 204 and an absorption layer 205 in the mesa part, which constitutes the central part of the element shown in the upper half of FIG. 3, is as represented by a solid line in the lower half. Thus, it is necessary to set the electric field higher in the multiplication layer to induce avalanche multiplication and, conversely, lower in the absorption layer to avoid avalanche multiplication and the occurrence of a tunneling current. This optimization of electric field distribution can be achieved by appropriately designing the carrier concentration in the field control layer. The electric field distribution in the mesa periphery in FIG. 3 is as represented by a broken line in the lower half of FIG. 3. Since the electric field here is lower than in the electric field distribution in the mesa part (solid line), the edge breakdown can be restrained and the dark current reduced. This is due to the absence of the absorption layer in the mesa periphery and to the effect of the 2-dimensional structure that the overall film thickness of the semiconductor on the mesa periphery is less than that of the semiconductor in the mesa part. Therefore, the voltage applied to the multiplication layer in the mesa periphery is reduced, and the electric field is lowered as a result.
By lowering the electric field intensity near the surface, it is made possible to reduce leak currents attributable to the surface state or any surface defect and accordingly the dark current while enhancing reliability at the same time.